View PI6C9911-5IJ_430066.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TEST
GND
REF
3F0
FB REF
Phase Freq Det
Filter FS
Vco and Time Unit Generator
4 3F1 4F0 5 6 7 8 9 10 11 12
3
2
1
32 31 30 29 28 27 2F0 GND 1F1 1F0 VCCN 1Q0 1Q1 GND GND
4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 SKEW SELECT MATRIX
4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1
4F1 VCCQ VCCN 4Q1 4Q0 GND GND
32-Pin J
Three Level Select Inputs
13 14 15 16 17
21 18 19 20
VCCN
FB
VCCN
3Q1
3Q0
2Q1
1
2Q0
2F1
26 25 24 23 22
TEST
VCCQ
FS
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E
5V High-Speed Programmable Skew Clock Buffers - SuperClock(R)
Product Features
* Four pairs of programmable skew outputs * User-selectable output functions: - Selectable skews - Inverted and noninverted - Operation at 1/2 and 1/4 input frequency - Operation at 2X and 4X input frequency * Low skew <100ps typical same pair, 250ps max. * Allow REF clock input to have Spread Spectrum modulation for EMI reduction * 2X, 4X, 1/2 and 1/4 outputs * 3-level inputs for skew and output frequency control * External feedback, internal loop filter * Low cycle-to-cycle Jitter: <25ps RMS * Duty cycle of output clock signals: 45% min. 55% max. * Same pinout as Cypress CY7B9911 * Available in 32-pin PLCC Package (J) * Output Operation 3.75 to 100 MHz for PI6C9911 3.75 to 125 MHz for PI6C9911E
Description
The PI6C9911 and PI6C9911E are low-skew, low jitter, 5V phaselock-loop (PLL) programmable skew clock drivers, for high-performance computing and networking applications. These parts offer user-selectable skew-control of 4 output pairs, providing the timing delays necessary to optimize high-performance clock-distribution circuits. Each output can be hardwired to one of nine delay or function configurations. Delay increments are determined by the input clock frequency and the configurations selected by the user. The PI6C9911 and PI6C9911E allow the REF clock input to have Spread Spectrum modulation for EMI reduction. Both buffers are pin-compatable with Cypresss RoboClock CY7B9911, but with improved AC/DC characteristics. The PI6C9911 and PI6C9911E also have the same pinout as Cypresss CY7B9911and with balanced output drive.
Logic Block Diagram
Pin Configuration
PS8451B
03/28/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock(R)
Pin Definitions
Signal Name REF FB FS 1F0, 1F1 2F0, 2F1 3F0, 3F1 4F0, 4F1 TEST 1Q0, 1Q1 2Q 0, 2Q 1 3Q 0, 3Q 1 4Q0, 4Q 1 VCCN VCCQ GND PWR O I I/O D e s cription Reference frequency input. This input supplies the frequency and timing reference which all functional variation is measured. PLL feedback input (typically connected to one of the eight outputs). Three- level frequency range select. See Table 1. Three- level function select inputs for output pair 1 (1Q0, 1Q 1). See Table 2. Three- level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2. Three- level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2. Three- level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2. Three- level select. See test mode section under the block diagram descriptions. Output pair 1. See Table 2. O utput pair 2. See Table 2. O utput pair 3. See Table 2. O utput pair 4. See Table 2. Power supply for output drivers. Power supply for internal circuitry. Ground
Block Diagram Description
Phase Frequency Detector and Filter These two blocks accept input signals from the reference frequency (REF) input and the feedback (FB) input and generate correction information to control the frequency of the Voltage-Controlled Oscillator (VCO). These blocks, along with the VCO, form a PhaseLocked Loop (PLL) that tracks the incoming REF signal. VCO and Time Unit Generator The VCO accepts analog control inputs from the PLL filter block and generates a frequency that is used by the time unit generator to create discrete time units that are selected in the skew mix matrix. The operational range of the VCO is determined by the FS control pin. The time unit (tU) is determined by the operating frequency of the device and the level of the FS pin as shown in Table 1. Skew Select Matrix The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout drivers (xQ0, xQ1), and two corresponding three-level function select (xF0, xF1) inputs. Table 2 shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0tU selected.
2
PS8451B
03/28/01
t0 +1tU
t0 +2tU
t0 +3tU
t0 +4tU
t0 +5tU
1Fx 2Fx (N/A) LL LM LH ML MM MH HL HM HH (N/A) (N/A) (N/A)
3Fx 4Fx LM LH (N/A) ML (N/A) MM (N/A) MH (N/A) HL
FB Input REF Input -6tU -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU
HM +6tU LL/HH DIVIDED HH INVERT
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output(4)
3
PS8451B 03/28/01
t0 +6tU
t0 -6tU
t0 -5tU
t0 -4tU
t0 -3tU
t0 -2tU
t0 -1tU
t0
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock(R)
Table 1. Frequency Range Select and tU Calculation(1)
FS(2,3) fNOM(M Hz) M in. LOW PI6C9911 MID HIGH LOW PI6C9911E MID HIGH 15 25 40 20 35 60 M ax. 30 50 100 40 70 125
Table 2. Programmable Skew Configurations(1)
Function Se le cts 1F1, 2F1, 3F1, 4F1 Output Functions 3Q0, 3Q1 4Q0, 4Q1 1F0, 2F0, 1Q0, 1Q1, 3F0, 4F0 2Q0, 2Q1 LOW LOW MID HIGH LOW - 4tU - 3tU - 2tU - 1tU - 0tU +1tU +2tU +3tU +4tU +2tU +4tU +6tU Divide by 4 Inverted
tU =
fNOM x N where N=
44 26 16 44 26 16
1
Approximate Fre que ncy (M Hz) at which tU = 1.0ns 22.7 38.5 62.5 22.7 38.5
Divide by 2 - 6tU - 4tU - 2tU
MID
MID HIGH LOW
HIGH
62.5
MID HIGH
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock(R)
Test Mode
The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the PI6C9911 to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a 100 ohm resistor. This will allow an external tester to change the state of these pins). If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode. In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own function select inputs (xF0 and xF1) and the waveform characteristics of the REF input.
Maximum Ratings
(Above which the useful life may be impaired) Storage Temperature ............................................ 65C to +150C Ambient Temperature with Power Applied ..............................................55C to +125C Supply Voltage to Ground Potential ....................... 0.5V to +7.0V DC Input Voltage .................................................... 0.5V to +7.0V Output Current into Outputs (LOW) ................................... 64mA Static Discharge Voltage (per MIL-STD-883, Method 3015) ................................. >2001V Latch-Up Current ............................................................ >200mA
Operating Range
Range Commercial Industrial
Notes for Tables on Pages 3 through 7: 1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connections to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FS is determined by the normal operating frequency (f NOM) of the VCO and the Time Unit Generator (see Logic Block Diagram). Nominal frequency (fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be fNOM when the output connected to FB is undivided.The frequency of REF and FB inputs will be f NOM/2 or fNOM /4 when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. When the FS pin is selected HIGH, the REF input must not transition upon power-up untill V CC has reached 4.3V. 4. FB connected to an output selected for zero skew (ie., xF1 = xF0 = MID). 6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshhold voltages vary as a percentage of VCC). Internal termination resistors hols unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 10. Test measurement levels are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless specified. 11. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 12. Skew is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 30pF and terminated with 50 to 2.06V. 13. tSKEWPR is defined as the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t U. 14. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted. 15. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 16. tDEV is the output-to-output skew between any 2 devices operating under the same conditions (VCC ambient temperature, air flow, etc.). 17. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t SKEW2 and tSKEW4 specifications. 18. Specified with outputs loaded with 30pF. Devices are terminated through 50 to 2.06V. 19. tPWH is measured at 2.0V. tPWL is measured at 0.8V 20. tORISE and tOFALL measured between 0.8V and 2.0V. 21. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t PD is within specified limits.
4
PS8451B 03/28/01
Ambie nt Te mpe rature 0C to +70C 40C to +85C
VCC 5V 10%
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock(R)
DC Characteristics Over the Operating Range
Symbol V OH V OL VIH VIL VIH3 VIM3 VIL3 IIN I3 Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage of REF, FB inputs Input LOW Voltage of REF, FB inputs Input HIGH Voltage of 3-level inputs TEST, FS, xFn(6) Input MID Voltage of 3-level inputs TEST, FS, xFn(6) Input LOW Voltage of 3-level inputs TEST, FS, xFn(6) Input Leakage Current of REF, FB inputs 3-Level Input DC Current (TEST, FS, nF 1:0) VIN = VCC or GND, VCC = Max VIN = VCC (HIGH level) VIN = VCC/2 (MID level) VIN = GND (LOW level) IOS ICCQ ICCN PD Short Circuit Current Operating Current usd by Internal Circuitry Output Buffer Current per Output Pair Power Dissipation per Output Pair VCC = Max. VOUT = GND (25 only) VCCN = VCCQ = Max. All Inputs Select Open VCCN = VCCQ = Max, IOUT = 0mA Input Selects Open, fMAX Min VCC Max Test Condition Vcc = Min., IOH = -16mA Vcc = Min., IOL = 46mA 2.0 -0.5 VCC-0.85V VCC/2 -0.5 Min. 2.4 0 . 45 V CC 0.8 V CC VCC/2 +0 . 5 0.85 10 20 0 50 200 -250 85 14 78 mW mA V Max. Units
Capacitance at REF and FB
Parame te r CIN D e s cription Input Capacitance Te s t Conditions TA = 25C, f = 1 MHz, VCC = 5.0V M ax. 10 Units pF
AC Test Loads and Waveforms (PI6C9911)
5V
3.0V
R1 R1 = 130 R2 = 91
2.0V V th = 1.5V 0.8V 0.0V
2.0V V = 1.5V th 0.8V
CL
CL = 30pF R2
(Includes fixture and probe capacitance)
1ns
TTL Input Test Waveform
1ns
TTL AC Test Load
(16)
5
PS8451B
03/28/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock(R)
Switching Characteristics over the Operating Range(2,10,11)
Parame te r De s cription Operating clock Frequency in MHz FS = LOW(1,2) FS = MID
(1,2)
PI6C9911-2 M in. 15 25 40 4.0 Typ. M ax. 30 50 100 15 25 40 4.0
PI6C9911-5 M in. Typ. M ax. 30 50 100 M in. 15 25 40 4.0 See Table 1
PI6C9911 Typ. M ax. 30 50 100
Units
FNOM tRPW H tRPW L tU tS K EW PR tS K EW 0 tS K EW 1 tS K EW 2 tS K EW 3 tS K EW 4 tDEV tP D t O DC V tP W H tP W L tO RIS E tO FALL t LO C K tJ R
MHz
FS = HIGH(1,2,3)
REF Pulse Width HIGH REF Pulse Width LOW Programmable Skew Unit Zero Output Matched- Pair Skew (xQ0, xQ1)(12,13) Zero Output Skew (All Outputs)(12,14) Output Skew (Rise- Rise, Fall- Fall, Same Class Outputs)(12,15) Output Skew (Rise- Fall, NominalInverted, Divided- Divided)(12,15) Output Skew (Rise- Rise, Fall- Fall, Different Class Outputs)(12,15) Output Skew (Rise- Fall, NominalDivided, Divided- Inverted)(12,15) Device- to- Device Skew(11,16) Propagation Delay, REF Rise to FB Rise Output Duty Cycle Variation(17) Output HIGH Time Deviation from 50%(18,19) Output LOW Time Deviation from 50%(18,19) Output Rise Time(18,20) Output Fall Time PLL Lock Time Cycle- to Cycle Output Jitter
(18,20) (21)
ns
0.05 0.10 0.25 0.30 0.25 0.50
0.20 0.25 0.5 0.5 0.5 0.9 0.75
0.1 0.25 0.6 0.50 0.50 0.50
0.25 0.5 0.7 1.2 0.9 1.2 1.25
0.1 0.3 0.6 1.0 0.7 1.2
0.25 0.75 1.0 1.5 1.2 1.7 1.65 ns
0.25 0.65
0 0
0.25 0.65 2.0 1.5
0.5 1.0
0 0
0.5 1.0 2.0 2.5
0.7 1.2
0.0 0.0
+0.7 +1.2 3.0 3.5
0.15 0.15
1.0 1.0
1.2 1.2 0.5 25
0.15 0.15
1.0 1.0
1.5 1.5 0.5 25 200
0.15 0.15
1.5 1.5
2.5 2.5 0.5 25 200 ms ps
RMS(11) Peak- to- Peak
(11)
200
6
PS8451B
03/28/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock(R)
Switching Characteristics over the Operating Range(2,10,11)
Parame te r D e s cription O perating clock Frequency in MHz FS = LO W(1,2) FS = MID
(1,2)
PI6C9911E-2 M in. 20 35 60 3.2 Typ. 40 70 125
PI6C9911E-5 20 35 60 3.2 See Table 1 40 70 125 20 35 60 3.2
PI6C9911E Typ. M ax. 40 70 125
M ax. M in.
Typ. M ax. M in.
Units
FNOM tRPW H tRPW L tU tS K EW PR tS K EW 0 tS K EW 1 tS K EW 2 tS K EW 3 tS K EW 4 tDEV tP D t O DC V tP W H tP W L tO RIS E tO FALL t LO C K tJ R
MHz
FS = HIGH(1,2,3)
REF Pulse Width HIGH REF Pulse Width LO W Programmable Skew Unit Zero O utput Matched- Pair Skew (xQ 0, xQ 1)(12,13) Zero O utput Skew (All O utputs)(12,14) O utput Skew (Rise- Rise, Fall- Fall, Same Class O utputs)(12,15) O utput Skew (Rise- Fall, NominalInverted, Divided- Divided)(12,15) O utput Skew (Rise- Rise, Fall- Fall, Different Class O utputs)(12,15) O utput Skew (Rise- Fall, NominalDivided, Divided- Inverted)(12,15) Device- to- Device Skew(11,16) Propagation Delay, REF Rise to FB Rise O utput Duty Cycle Variation(17) O utput HIGH Time Deviation from 50%(18,19) O utput LO W Time Deviation from 50%(18,19) O utput Rise Time(18,20) O utput Fall Time PLL Lock Time Cycle- to Cycle O utput Jitter
(18,20) (21)
ns
0.05 0.10 0.25 0.30 0.25 0.50
0.20 0.25 0.5 0.5 0.5 0.9 0.75
0.1 0.25 0.6 0.50 0.50 0.50
0.25 0.5 0.7 1.2 0.9 1.2 1.25
0.1 0.3 0.6 1.0 0.7 1.2
0.25 0.75 1.0 1.5 1.2 1.7 1.65 ns
0.25 0.65
0 0
0.25 0.65 2.0 1.5
0.5 1.0
0 0
0.5 1.0 2.0 2.5
0.7 1.2
0.0 0.0
+0.7 +1.2 3.0 3.5
0.15 0.15
(11)
1.0 1.0
1.2 1.2 0.5 25 200
0.15 0.15
1.0 1.0
1.5 1.5 0.5 25 200
0.15 0.15
1.5 1.5
2.5 2.5 0.5 25 200 ms ps
RMS
Peak- to- Peak(11)
7
PS8451B
03/28/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
AC Timing Diagrams
REF DIVIDED BY 4
REF DIVIDED BY 2
INVERTED Q
OTHER Q
REF
FB
Q
t
RPWH
t
PD
t
REF
t
t
t
t
SKEWPR,
SKEW3,4
SKEW3,4
SKEW0,1
t
ODCV
8
t
RPWL
t
SKEW3,4
t
t
SKEW2
ODCV
t
t
SKEWPR,
SKEW0,1
PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock(R)
t
SKEW2
t
t
SKEW2,4
SKEW3,4
t
JR
PS8451B
03/28/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E 5V High Speed Programmable Skew Clock Buffers - SuperClock(R)
Package Diagram 32-Pin PLCC (J)
.045 1.143 Typ. .050 1.27 BSC
Pin 1 .025 0.635 Typ.
.585 .595 14.859 15.113
.547 .553 13.894 14.046
.045 Typ. 1.143
.490 .530 .026 .032 0.661 12.446 13.462
.447 .453 11.354 11.506 .485 .495 12.319 12.573
0.812
X.XX X.XX .100 .140 2.450 3.556 .065 .095 .013 0.331 .021 0.533 .015 0.381 Min. .390 .430 9.906 10.922 1.524 2.413
DENOTES DIMENSIONS IN MILLIMETERS
Ordering Information
Part Numbe r PI6C9911- 2J PI6C9911- 5J PI6C9911J PI6C9911- 5IJ PI6C9911IJ PI6C9911E- 2J PI6C9911E- 5J PI6C9911EJ PI6C9911E- 5IJ PI6C9911EIJ Accuracy 250ps 500ps 750ps 500ps 750ps 250ps 500ps 750ps 500ps 750ps Package Ope rating Te mpe rature Commercial Industrial 32- Pin PLCC Commercial Industrial
Pericom Semiconductor Corporation 2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
9
PS8451B 03/28/01

▲Up To Search▲

Price & Availability of PI6C9911-5IJ

	To Download PI6C9911-5IJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .